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» Design Challenges for High Performance Nano-Technology
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ANCS
2006
ACM
15 years 3 months ago
Efficient memory utilization on network processors for deep packet inspection
Deep Packet Inspection (DPI) refers to examining both packet header and payload to look for predefined patterns, which is essential for network security, intrusion detection and c...
Piti Piyachon, Yan Luo
ICDCSW
2007
IEEE
15 years 6 months ago
UBCA: Utility-Based Clustering Architecture for Peer-to-Peer Systems
Peer-to-Peer (P2P) systems are currently used in a variety of applications. File sharing applications and ad hoc networking have fueled the usage of these systems. P2P systems gen...
Brent Lagesse, Mohan Kumar
TPDS
2010
174views more  TPDS 2010»
14 years 10 months ago
Parallel Two-Sided Matrix Reduction to Band Bidiagonal Form on Multicore Architectures
The objective of this paper is to extend, in the context of multicore architectures, the concepts of tile algorithms [Buttari et al., 2007] for Cholesky, LU, QR factorizations to t...
Hatem Ltaief, Jakub Kurzak, Jack Dongarra
PLDI
2012
ACM
13 years 2 months ago
Adaptive input-aware compilation for graphics engines
While graphics processing units (GPUs) provide low-cost and efficient platforms for accelerating high performance computations, the tedious process of performance tuning required...
Mehrzad Samadi, Amir Hormati, Mojtaba Mehrara, Jan...
AINA
2005
IEEE
15 years 5 months ago
Periodic Contention-Free Multiple Access for Power Line Communication Networks
— There is industrial intent to use Powerline Communication (PLC) PLC networks in the home for delivery of multimedia data, with associated challenging quality of service (QoS) r...
Yu-Ju Lin, Haniph A. Latchman, Jonathan C. L. Liu,...