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» Design Challenges for High Performance Nano-Technology
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EDCC
2006
Springer
15 years 3 months ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...
DILS
2005
Springer
15 years 5 months ago
PLATCOM: Current Status and Plan for the Next Stages
We have been developing a system for comparing multiple genomes, PLATCOM, where users can choose genomes of their choice freely and perform analysis of the selected genomes with a...
Kwangmin Choi, Jeong-Hyeon Choi, Amit Saple, Zhipi...
IPPS
2002
IEEE
15 years 4 months ago
Can User-Level Protocols Take Advantage of Multi-CPU NICs?
Modern high speed interconnects such as Myrinet and Gigabit Ethernet have shifted the bottleneck in communication from the interconnect to the messaging software at the sending an...
Piyush Shivam, Pete Wyckoff, Dhabaleswar K. Panda
SIGCOMM
2005
ACM
15 years 5 months ago
One more bit is enough
Achieving efficient and fair bandwidth allocation while minimizing packet loss in high bandwidth-delay product networks has long been a daunting challenge. Existing endto-end cong...
Yong Xia, Lakshminarayanan Subramanian, Ion Stoica...
DAC
2007
ACM
16 years 26 days ago
Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction
The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of ti...
Zhuo Feng, Peng Li, Yaping Zhan