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» Design Challenges for High Performance Nano-Technology
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DAC
2007
ACM
15 years 10 months ago
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characte...
Kunhyuk Kang, Kee-Jong Kim, Ahmad E. Islam, Muhamm...
INFOCOM
2007
IEEE
15 years 3 months ago
On the Extreme Parallelism Inside Next-Generation Network Processors
Next-generation high-end Network Processors (NP) must address demands from both diversified applications and ever-increasing traffic pressure. One major challenge is to design an e...
Lei Shi, Yue Zhang 0006, Jianming Yu, Bo Xu, Bin L...
ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
15 years 3 months ago
SODA: A Low-power Architecture For Software Radio
The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a ...
Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scot...
ICAC
2009
IEEE
15 years 4 months ago
Self-correlating predictive information tracking for large-scale production systems
Automatic management of large-scale production systems requires a continuous monitoring service to keep track of the states of the managed system. However, it is challenging to ac...
Ying Zhao, Yongmin Tan, Zhenhuan Gong, Xiaohui Gu,...
DATE
2008
IEEE
182views Hardware» more  DATE 2008»
15 years 3 months ago
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking
— As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to ...
Swaroop Ghosh, Patrick Ndai, Kaushik Roy