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ISPD
2011
ACM
253views Hardware» more  ISPD 2011»
14 years 8 months ago
Assembling 2D blocks into 3D chips
Three-dimensional ICs promise to significantly extend the scale of system integration and facilitate new-generation electronics. However, progress in commercial 3D ICs has been s...
Johann Knechtel, Igor L. Markov, Jens Lienig
GLOBECOM
2007
IEEE
15 years 11 months ago
Non-Cooperative Design of Translucent Networks
This paper introduces a new game theoretic formulation for the design and routing of resilient and translucent networks. An integer linear programming (ILP) modeling is also presen...
Benoît Châtelain, Shie Mannor, Fran&cc...
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
15 years 3 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
ASPDAC
2004
ACM
96views Hardware» more  ASPDAC 2004»
15 years 10 months ago
Register binding and port assignment for multiplexer optimization
- Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult pro...
Deming Chen, Jason Cong
ISVLSI
2007
IEEE
181views VLSI» more  ISVLSI 2007»
15 years 11 months ago
Code-coverage Based Test Vector Generation for SystemC Designs
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
Alair Dias Jr., Diógenes Cecilio da Silva J...