123 search results - page 1 / 25 » Design For Testability Method for CML Digital Circuits |
68
Voted
DATE
1999
IEEE
15 years 1 months ago
1999
IEEE
This paper presents a new Design for Testability (DFT) technique for Current-Mode Logic (CML) circuits. This new technique, with little overhead, using built-in detectors, monitor...
75
Voted
DSD
2008
IEEE
15 years 4 months ago
2008
IEEE
Testability is one of the most important factors that are considered during design cycle along with reliability, speed, power consumption, cost and other factors important for a c...
97
Voted
WCE
2007
14 years 10 months ago
2007
Improving testability during the early stages of High-level synthesis has several advantages including reduced test hardware overhead and design iterations. Recently, BIST techniq...
ISCAS
2003
IEEE
15 years 2 months ago
2003
IEEE
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
105
click to vote
INTEGRATION
2006
14 years 9 months ago
2006
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...