5107 search results - page 434 / 1022 » Design Issue Of ECTST |
141
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DATE
2009
IEEE
15 years 11 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
137
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GLVLSI
2009
IEEE
15 years 11 months ago
2009
IEEE
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
152
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ICC
2009
IEEE
15 years 11 months ago
2009
IEEE
—This paper presents a novel cross-layer design for joint power and end-to-end rate control optimization in DSCDMA wireless networks, along with a detailed implementation and eva...
148
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WCRE
2009
IEEE
15 years 11 months ago
2009
IEEE
—During the evolution of a software system, a large amount of information, which is not always directly related to the source code, is produced. Several researchers have provided...
158
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NOCS
2009
IEEE
15 years 11 months ago
2009
IEEE
With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distrib...