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ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
15 years 1 months ago
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
ICCAD
2000
IEEE
115views Hardware» more  ICCAD 2000»
15 years 2 months ago
Challenges and Opportunities in Broadband and Wireless Communication Designs
Communication designs form the fastest growing segment of the semiconductor market. Both network processors and wireless chipsets have been attracting a great deal of research att...
Jan M. Rabaey, Miodrag Potkonjak, Farinaz Koushanf...
DAC
2004
ACM
15 years 10 months ago
Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs
The negative effect of electromigration on signal and power line lifetime and functional reliability is an increasingly important problem for the physical design of integrated cir...
Goeran Jerke, Jürgen Scheible, Jens Lienig
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 2 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
CHI
2009
ACM
15 years 10 months ago
Reduced empathizing skills increase challenges for user-centered design
User-Centered Design is surprisingly difficult. One of the biggest issues, certainly for those with no HCI or usability experience, is a lack of appreciation of how users think an...
William Hudson