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ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
15 years 9 months ago
Rescue: A Microarchitecture for Testability and Defect Tolerance
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
Ethan Schuchman, T. N. Vijaykumar
ISPAN
2005
IEEE
15 years 9 months ago
Process Scheduling for the Parallel Desktop
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...
Eitan Frachtenberg
ISPASS
2005
IEEE
15 years 9 months ago
Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites
Performance evaluation using only a subset of programs from a benchmark suite is commonplace in computer architecture research. This is especially true during early design space e...
Aashish Phansalkar, Ajay Joshi, Lieven Eeckhout, L...
MICRO
2005
IEEE
110views Hardware» more  MICRO 2005»
15 years 9 months ago
Scalable Store-Load Forwarding via Store Queue Index Prediction
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
Tingting Sha, Milo M. K. Martin, Amir Roth
SP
2005
IEEE
188views Security Privacy» more  SP 2005»
15 years 9 months ago
BIND: A Fine-Grained Attestation Service for Secure Distributed Systems
In this paper, we propose BIND (Binding Instructions aNd Data),1 a fine-grained attestation service for securing distributed systems. Code attestation has recently received consi...
Elaine Shi, Adrian Perrig, Leendert van Doorn