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» Design Issues and Tradeoffs for Write Buffers
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ISCAS
2005
IEEE
138views Hardware» more  ISCAS 2005»
13 years 12 months ago
Transition time bounded low-power clock tree construction
— Recently power becomes a significant issue in clock network design for high-performance ICs because the clock network consumes a large portion of the total power in the whole s...
Min Pan, Chris C. N. Chu, J. Morris Chang
DSN
2008
IEEE
14 years 22 days ago
Combined circuit and microarchitecture techniques for effective soft error robustness in SMT processors
As semiconductor technology scales, reliability is becoming an increasingly crucial challenge in microprocessor design. The rSRAM and voltage scaling are two promising circuit-lev...
Xin Fu, Tao Li, José A. B. Fortes
GLOBECOM
2007
IEEE
14 years 18 days ago
Network-Calculus-Based Analysis of Power Management in Video Sensor Networks
— This paper considers two important issues for video sensor network, (1) timely delivery of captured video stream and (2) energy-efficient network design. Based on network calc...
Yanchuan Cao, Yuan Xue, Yi Cui
DAC
2012
ACM
11 years 8 months ago
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vij...
ICS
2011
Tsinghua U.
12 years 9 months ago
Hystor: making the best use of solid state drives in high performance storage systems
With the fast technical improvement, flash memory based Solid State Drives (SSDs) are becoming an important part of the computer storage hierarchy to significantly improve perfo...
Feng Chen, David A. Koufaty, Xiaodong Zhang