Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous design, this requires the consideration o...
Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhi...
The demand for high performance has driven acyclic computation accelerators into extensive use in modern embedded and desktop architectures. Accelerators that are ideal from a sof...
: On-chipimplementationofmultiprocessorsystemsneedstoplanarisetheinterconnect networks onto the silicon floorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor ...
New static source routing algorithms for High Performance Computing (HPC) are presented in this work. The target parallel architectures are based on the commonly used fattree netw...
As minimum feature sizes continue to shrink, patterned features have become significantly smaller than the wavelength of light used in optical lithography. As a result, the requir...
Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, J...