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ICCAD
2007
IEEE
128views Hardware» more  ICCAD 2007»
15 years 10 months ago
Module assignment for pin-limited designs under the stacked-Vdd paradigm
Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficient...
Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar
DAC
2001
ACM
16 years 2 months ago
Semi-Formal Test Generation with Genevieve
This paper describes the first application of the Genevieve test generation methodology. The Genevieve approach uses semi-formal techniques derived from "model-checking"...
Julia Dushina, Mike Benjamin, Daniel Geist
VLSID
2005
IEEE
100views VLSI» more  VLSID 2005»
16 years 2 months ago
A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model
Buffer insertion method plays a great role in modern VLSI design. Many buffer insertion algorithms have been proposed in recent years. However, most of them used simplified delay ...
Yibo Wang, Yici Cai, Xianlong Hong
DAC
2007
ACM
16 years 2 months ago
IPR: An Integrated Placement and Routing Algorithm
Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all...
Min Pan, Chris C. N. Chu
ASAP
2005
IEEE
165views Hardware» more  ASAP 2005»
15 years 7 months ago
CONAN - A Design Exploration Framework for Reliable Nano-Electronics
In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our...
Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici,...