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DAC
2009
ACM
15 years 5 months ago
RegPlace: a high quality open-source placement framework for structured ASICs
Structured ASICs have recently emerged as an exciting alternative to ASIC or FPGA design style as they provide a new trade-off between the high performance of ASIC design and low ...
Ashutosh Chakraborty, Anurag Kumar, David Z. Pan
ASPDAC
2007
ACM
106views Hardware» more  ASPDAC 2007»
15 years 3 months ago
Bisection Based Placement for the X Architecture
Rising interconnect delay and power consumption have motivated the investigation of alternative integrated circuit routing architectures. In particular, the X Architecture, which ...
Satoshi Ono, Sameer Tilak, Patrick H. Madden
CSB
2004
IEEE
123views Bioinformatics» more  CSB 2004»
15 years 5 months ago
A New Hardware Architecture for Genomic and Proteomic Sequence Alignment
We describe a novel hardware architecture for genomic and proteomic sequence alignment which achieves a speed-up of two to three orders of magnitude over Smith-Waterman dynamic pr...
Greg Knowles, Paul Gardner-Stephen
TPDS
2002
105views more  TPDS 2002»
15 years 1 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
15 years 1 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri