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ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
15 years 7 months ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
109
Voted
DAC
2005
ACM
15 years 3 months ago
Performance space modeling for hierarchical synthesis of analog integrated circuits
Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient ...
Georges G. E. Gielen, Trent McConaghy, Tom Eeckela...
117
Voted
NOCS
2007
IEEE
15 years 8 months ago
NoC Design and Implementation in 65nm Technology
As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent...
Antonio Pullini, Federico Angiolini, Paolo Meloni,...
IAT
2003
IEEE
15 years 7 months ago
SIMPLE - A Multi-Agent System for Simultaneous and Related Auctions
This work describes a multi-agent architecture and strategy for trade in simultaneous and related auctions. The proposed SIMPLE Agency combines an integer programming model, machi...
Ruy Luiz Milidiú, Taciana Melcop, Frederico...
122
Voted
DAC
2003
ACM
16 years 2 months ago
Multilevel global placement with retiming
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...
Jason Cong, Xin Yuan