473 search results - page 12 / 95 » Design Methodologies for Noise in Digital Integrated Circuit... |
ICCAD
2001
IEEE
15 years 8 months ago
2001
IEEE
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling a...
CHINAF
2006
14 years 11 months ago
2006
: With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical d...
105
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DAC
2007
ACM
16 years 22 days ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
DELTA
2006
IEEE
15 years 5 months ago
2006
IEEE
In high speed digital circuits, the inductive effect is more dominant compared to capacitive effect. In particular, as the technology is shrinking, the spacing between interconnec...
DATE
2010
IEEE
15 years 4 months ago
2010
IEEE
Abstract—This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultr...