473 search results - page 17 / 95 » Design Methodologies for Noise in Digital Integrated Circuit... |
MR
2002
14 years 11 months ago
2002
ESD protection design for CMOS RF integrated circuits is proposed in this paper by using the stacked polysilicon diodes as the input ESD protection devices to reduce the total inp...
ASPDAC
2007
ACM
15 years 3 months ago
2007
ACM
The scaling of CMOS technology into the nanometer era enables the fabrication of highly integrated systems, which increasingly contain analog and/or RF parts. However, scaling into...
JETC
2008
14 years 10 months ago
2008
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
WCE
2007
15 years 27 days ago
2007
—Clock jitter and its effects on signal-to-noise ratio (SNR) were widely investigated in the published literatures. However, most of the issues mainly focused on white-Gaussian-n...
EIT
2008
IEEE
15 years 6 months ago
2008
IEEE
—A new biasing technique called “local biasing” of transistors is used to design analog integrated circuit amplifiers, or any other analog ICs. The technique is based on desi...