473 search results - page 54 / 95 » Design Methodologies for Noise in Digital Integrated Circuit... |
DAC
2005
ACM
15 years 1 months ago
2005
ACM
Traditional corner analysis fails to guarantee a target yield for a given performance metric. However, recently proposed solutions, in the form of statistical timing analysis, whi...
IPPS
2010
IEEE
14 years 9 months ago
2010
IEEE
This paper focuses on parallelization of the classic static timing analysis (STA) algorithm for verifying timing characteristics of digital integrated circuits. Given ever-increasi...
106
click to vote
EURODAC
1994
IEEE
15 years 4 months ago
1994
IEEE
synchronisation also play a fundamental role in overall system robustness. ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Interference (EMI) issues also have to be conside...
135
click to vote
CVPR
2008
IEEE
15 years 1 months ago
2008
IEEE
Most digital still color cameras use a single electronic sensor (CCD or CMOS) overlaid with a color filter array. At each pixel location only one color sample is taken, and the ot...
120
click to vote
DATE
2009
IEEE
15 years 3 months ago
2009
IEEE
In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential ci...