473 search results - page 81 / 95 » Design Methodologies for Noise in Digital Integrated Circuit... |
GLVLSI
2002
IEEE
15 years 4 months ago
2002
IEEE
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
ICCD
2005
IEEE
15 years 8 months ago
2005
IEEE
Abstract— Noise induced by impedance discontinuities from VLSI packaging is one of the leading challenges facing system level designers in the next decade. The performance of IC ...
100
click to vote
DAC
2006
ACM
15 years 5 months ago
2006
ACM
Several emerging Design-for-Debug (DFD) methodologies are addressing silicon debug by making internal signal values and other data observable. Most of these methodologies require ...
DAC
2012
ACM
13 years 2 months ago
2012
ACM
In this work, we propose a fast and accurate chip/package thermomechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also present a design optimization meth...
FPGA
2000
ACM
15 years 3 months ago
2000
ACM
With increased logic density due to the shift towards Deep Submicron technologies (DSM), FPGAs have become a viable option for implementing large designs. However, most commercial...