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ASPLOS
2009
ACM
16 years 8 days ago
Accelerating critical section execution with asymmetric multi-core architectures
To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In mult...
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi...
DALT
2004
Springer
15 years 5 months ago
Reasoning About Agents' Interaction Protocols Inside DCaseLP
Engineering systems of heterogeneous agents is a difficult task; one of the ways for achieving the successful industrial deployment of agent technology is the development of engine...
Matteo Baldoni, Cristina Baroglio, Ivana Gungui, A...
HPDC
2005
IEEE
15 years 5 months ago
A new metric for robustness with application to job scheduling
Scheduling strategies for parallel and distributed computing have mostly been oriented toward performance, while striving to achieve some notion of fairness. With the increase in ...
Darin England, Jon B. Weissman, Jayashree Sadagopa...
SAMOS
2004
Springer
15 years 5 months ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope
ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
15 years 5 months ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen