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CASES
2009
ACM
15 years 3 months ago
A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...
128
Voted
TCS
2002
15 years 2 days ago
CASL: the Common Algebraic Specification Language
The Common Algebraic Specification Language Casl is an expressive language for the formal specification of functional requirements and modular design of software. It has been desi...
Egidio Astesiano, Michel Bidoit, Hélè...
101
Voted
ISSTA
2010
ACM
15 years 4 months ago
Testing system virtual machines
Virtual machines offer the ability to partition the resources of a physical system and to create isolated execution environments. The development of virtual machines is a very ch...
Lorenzo Martignoni, Roberto Paleari, Giampaolo Fre...
CODES
2003
IEEE
15 years 5 months ago
Security wrappers and power analysis for SoC technologies
Future wireless internet enabled devices will be increasingly powerful supporting many more applications including one of the most crucial, security. Although SoCs offer more resi...
Catherine H. Gebotys, Y. Zhang
IEEECIT
2010
IEEE
14 years 11 months ago
CFCSS without Aliasing for SPARC Architecture
With the increasing popularity of COTS (commercial off the shelf) components and multi-core processor in space and aviation applications, software fault tolerance becomes attracti...
Chao Wang, Zhongchuan Fu, Hongsong Chen, Wei Ba, B...