605 search results - page 32 / 121 » Design Principles for Combiners with Memory |
RTAS
2010
IEEE
14 years 8 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...
ECML
2007
Springer
15 years 3 months ago
2007
Springer
We present Policy Gradient Actor-Critic (PGAC), a new model-free Reinforcement Learning (RL) method for creating limited-memory stochastic policies for Partially Observable Markov ...
CF
2007
ACM
15 years 1 months ago
2007
ACM
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
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ARCS
2009
Springer
15 years 4 months ago
2009
Springer
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
ICCAD
2008
IEEE
15 years 6 months ago
2008
IEEE
— With process variation becoming a growing concern in deep submicron technologies, the ability to efficiently obtain an accurate estimate of failure probability of SRAM compone...