Sciweavers

1635 search results - page 164 / 327
» Design Productivity for Configurable Computing
Sort
View
VLSID
2004
IEEE
170views VLSI» more  VLSID 2004»
16 years 2 months ago
On-chip networks: A scalable, communication-centric embedded system design paradigm
As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts...
Jörg Henkel, Srimat T. Chakradhar, Wayne Wolf
TASE
2011
IEEE
14 years 9 months ago
KnitSketch: A Sketch Pad for Conceptual Design of 2D Garment Patterns
—In this paper, we present a new sketch-based system — KnitSketch, to improve the efficiency of process planning for knitting garments at an early design stage. The KnitSketch...
Cui-Xia Ma, Yong-Jin Liu, Hai-Yan Yang, Dong-Xing ...
DAC
2007
ACM
16 years 2 months ago
Gate Sizing For Cell Library-Based Designs
With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with library-based methodologies. In spite of this shif...
Shiyan Hu, Mahesh Ketkar, Jiang Hu
ISLPED
2010
ACM
170views Hardware» more  ISLPED 2010»
15 years 2 months ago
Low-power sub-threshold design of secure physical unclonable functions
The unique and unpredictable nature of silicon enables the use of physical unclonable functions (PUFs) for chip identification and authentication. Since the function of PUFs depen...
Lang Lin, Daniel E. Holcomb, Dilip Kumar Krishnapp...
ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
15 years 6 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...