Sciweavers

1635 search results - page 289 / 327
» Design Productivity for Configurable Computing
Sort
View
ISCAS
2005
IEEE
156views Hardware» more  ISCAS 2005»
15 years 5 months ago
Optimal 2 sub-bank memory architecture for bit plane coder of JPEG2000
—JPEG2000 image compression standard is designed to cater the needs of a large span of applications including numerous consumer products. However, its use is still restricted due...
Amit Kumar Gupta, Saeid Nooshabadi, David S. Taubm...
RTCSA
2005
IEEE
15 years 5 months ago
An On-Chip Garbage Collection Coprocessor for Embedded Real-Time Systems
Garbage collection considerably increases programmer productivity and software quality. However, it is difficult to implement garbage collection both efficiently and suitably fo...
Matthias Meyer
DOLAP
2004
ACM
15 years 5 months ago
Developing a characterization of business intelligence workloads for sizing new database systems
Computer system sizing involves estimating the amount of hardware resources needed to support a new workload not yet deployed in a production environment. In order to determine th...
Ted J. Wasserman, Patrick Martin, David B. Skillic...
SIGUCCS
2004
ACM
15 years 5 months ago
Online solutions: looking to the future of knowledgeBase management
The Princeton University Help Desk KnowledgeBase (KB) is a searchable online information system that publishes Princetonspecific computer solutions to better serve the University ...
Annie Saunders
EUC
2004
Springer
15 years 5 months ago
Non-uniform Set-Associative Caches for Power-Aware Embedded Processors
Abstract. Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Especially, as the transistor supply voltag...
Seiichiro Fujii, Toshinori Sato