50 search results - page 1 / 10 » Design Rewiring Using ATPG |
63
Voted
ITC
2002
IEEE
15 years 2 months ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
83
Voted
TNN
2010
14 years 4 months ago
2010
A distributed and locally reprogrammable address event receiver has been designed, in which incoming addressevents are monitored simultaneously by all synapses, allowing for arbitr...
DSVIS
2008
Springer
14 years 11 months ago
2008
Springer
The design of interactive software that populates an ambient space is a complex and ad-hoc process with traditional software development approaches. In an ambient space, important ...
100
Voted
TCAD
2011
14 years 4 months ago
2011
—This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered launch-oncapture (LOC) scheme followed by the one-hot LOC scheme for testing ...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—Redundancy Addition and Removal (RAR) is a restructuring technique used in the synthesis and optimization of logic designs. It can remove an existing target wire and add an alte...