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79
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MICRO
2008
IEEE
84views Hardware» more  MICRO 2008»
15 years 7 months ago
A performance-correctness explicitly-decoupled architecture
Optimizing the common case has been an adage in decades of processor design practices. However, as the system complexity and optimization techniques’ sophistication have increas...
Alok Garg, Michael C. Huang
RECONFIG
2008
IEEE
268views VLSI» more  RECONFIG 2008»
15 years 7 months ago
Parametric, Secure and Compact Implementation of RSA on FPGA
1 We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The desig...
Ersin Oksuzoglu, Erkay Savas
107
Voted
CODES
2007
IEEE
15 years 7 months ago
Performance improvement of block based NAND flash translation layer
With growing capacities of flash memories, an efficient layer to manage read and write access to flash is required. NFTL is a widely used block based flash translation layer de...
Siddharth Choudhuri, Tony Givargis
105
Voted
CODES
2007
IEEE
15 years 7 months ago
Probabilistic performance risk analysis at system-level
We present a novel hybrid approach for performance analysis of a system design. Unlike other approaches in this area, in this paper we do not focus on the determination of pessimi...
Alexander Viehl, Markus Schwarz, Oliver Bringmann,...
125
Voted
ISORC
2007
IEEE
15 years 7 months ago
Evaluating Real-Time Publish/Subscribe Service Integration Approaches in QoS-Enabled Component Middleware
As quality of service (QoS)-enabled component middleware technologies gain widespread acceptance to build distributed real-time and embedded (DRE) systems, it becomes necessary fo...
Gan Deng, Ming Xiong, Aniruddha S. Gokhale, George...