796 search results - page 113 / 160 » Design Space Exploration for Dynamically Reconfigurable Arch... |
ICCAD
2004
IEEE
15 years 6 months ago
2004
IEEE
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
ICPR
2002
IEEE
15 years 11 months ago
2002
IEEE
This paper proposes a system architecture for event recognition that integrates information from multiple sources (e.g., gesture and speech recognition from distributed sensors in...
CSREAESA
2006
14 years 11 months ago
2006
Modern processors have a small on-chip local memory for instructions. Usually it is in the form of a cache but in some cases it is an addressable memory. In the latter, the user is...
ARC
2009
Springer
15 years 4 months ago
2009
Springer
Abstract. Most hardware/software codesigns of Elliptic Curve Cryptography only have one central control unit, typically a 32 bit or 8 bit processor core. With the ability of integr...
CSE
2009
IEEE
15 years 4 months ago
2009
IEEE
—In this paper we present a design methodology for the identification and development of a suitable hardware platform (including dedicated hardware accelerators) for the data pl...