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TVLSI
1998
109views more  TVLSI 1998»
14 years 9 months ago
Power estimation of embedded systems: a hardware/software codesign approach
— The need for low-power embedded systems has become very significant within the microelectronics scenario in the most recent years. A power-driven methodology is mandatory duri...
William Fornaciari, Paolo Gubian, Donatella Sciuto...
ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
15 years 6 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
TC
2008
14 years 9 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
MICRO
2009
IEEE
137views Hardware» more  MICRO 2009»
15 years 4 months ago
ESKIMO: Energy savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem
Dynamic Random Access Memory (DRAM) is used as the bulk of the main memory in most computing systems and its energy and power consumption has become a first-class design considera...
Ciji Isen, Lizy Kurian John
DAC
2007
ACM
15 years 1 months ago
Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies
This paper presents MOJITO, a system which optimizes across thousands of analog circuit topologies simultaneously, and returns a set of sized topologies that collectively provide ...
Trent McConaghy, Pieter Palmers, Georges G. E. Gie...