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DAC
2007
ACM
15 years 10 months ago
Gate Sizing For Cell Library-Based Designs
With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with library-based methodologies. In spite of this shif...
Shiyan Hu, Mahesh Ketkar, Jiang Hu
HPCA
2011
IEEE
14 years 1 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
DAGSTUHL
2011
13 years 9 months ago
Interactive Isocontouring of High-Order Surfaces
Scientists and engineers are making increasingly use of hp-adaptive discretization methods to compute simulations. While techniques for isocontouring the high-order data generated...
Christian Azambuja Pagot, Joachim E. Vollrath, Fil...
SBACPAD
2004
IEEE
97views Hardware» more  SBACPAD 2004»
14 years 11 months ago
IATO: A Flexible EPIC Simulation Environment
High-performance superscalar processors are designed with the help of complex simulation environment. The simulation infrastructure permits to validate the processor instruction s...
Amaury Darsch, André Seznec
DATE
2010
IEEE
202views Hardware» more  DATE 2010»
15 years 2 months ago
FlashPower: A detailed power model for NAND flash memory
Abstract— Flash memory is widely used in consumer electronics products, such as cell-phones and music players, and is increasingly displacing hard disk drives as the primary stor...
Vidyabhushan Mohan, Sudhanva Gurumurthi, Mircea R....