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CODES
2009
IEEE
15 years 2 months ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...
89
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ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
15 years 6 months ago
Application-specific customization of parameterized FPGA soft-core processors
Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are p...
David Sheldon, Rakesh Kumar, Roman L. Lysecky, Fra...
ISCA
2002
IEEE
91views Hardware» more  ISCA 2002»
15 years 2 months ago
Slack: Maximizing Performance Under Technological Constraints
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
Brian A. Fields, Rastislav Bodík, Mark D. H...
CSCW
2008
ACM
14 years 11 months ago
Understanding collective play in an urban screen game
In recent years there has been a growing interest in urban screen applications. While there have been several deployments of these technologies in our urban environments, surprisi...
Kenton O'Hara, Maxine Glancy, Simon Robertshaw
HPCA
2012
IEEE
13 years 5 months ago
System-level implications of disaggregated memory
Recent research on memory disaggregation introduces a new architectural building block—the memory blade—as a cost-effective approach for memory capacity expansion and sharing ...
Kevin T. Lim, Yoshio Turner, Jose Renato Santos, A...