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FPL
2004
Springer
83views Hardware» more  FPL 2004»
15 years 3 months ago
System-Level Modeling of Dynamically Reconfigurable Co-processors
Dynamically reconfigurable co-processors (DRCs) are interesting design alternatives when both flexibility and performance are concerns. However, it is difficult to study the perfor...
Yang Qu, Kari Tiensyrjä, Kostas Masselos
WCRE
2007
IEEE
15 years 4 months ago
EvoSpaces Visualization Tool: Exploring Software Architecture in 3D
The EvoSpaces reverse-engineering tool represents the architecture and metrics of complex software systems as 3D software cities. By navigating and interacting with this world, th...
Sazzadul Alam, Philippe Dugerdil
CODES
2009
IEEE
15 years 1 months ago
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
Vincenzo Rana, Srinivasan Murali, David Atienza, M...
IEEECIT
2010
IEEE
14 years 7 months ago
SESAM: An MPSoC Simulation Environment for Dynamic Application Processing
Future systems will have to support multiple and concurrent dynamic compute-intensive applications, while respecting real-time and energy consumption constraints. With the increase...
Nicolas Ventroux, Alexandre Guerre, Tanguy Sassola...
JRTIP
2008
249views more  JRTIP 2008»
14 years 9 months ago
Model-based mapping of reconfigurable image registration on FPGA platforms
Abstract Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficie...
Mainak Sen, Yashwanth Hemaraj, William Plishker, R...