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ICCD
2004
IEEE
125views Hardware» more  ICCD 2004»
15 years 6 months ago
IPC Driven Dynamic Associative Cache Architecture for Low Energy
Existing schemes for cache energy optimization incorporate a limited degree of dynamic associativity: either direct mapped or full available associativity (say 4-way). In this pap...
Sriram Nadathur, Akhilesh Tyagi
TECS
2008
119views more  TECS 2008»
14 years 9 months ago
Fast exploration of bus-based communication architectures at the CCATB abstraction
straction SUDEEP PASRICHA and NIKIL DUTT University of California, Irvine and MOHAMED BEN-ROMDHANE Newport Media Inc. Currently, system-on-chip (SoC) designs are becoming increasin...
Sudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane
CHI
1998
ACM
15 years 2 months ago
Exploring Browser Design Trade-Offs Using a Dynamical Model of Optimal Information Foraging
Designers and researchers of human-computer interaction need tools that permit the rapid exploration and management of hypotheses about complex interactions of designs, task condi...
Peter Pirolli
DAC
2000
ACM
15 years 10 months ago
Hardware-software co-design of embedded reconfigurable architectures
In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically re...
Yanbing Li, Tim Callahan, Ervan Darnell, Randolph ...
ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
14 years 11 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy