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DAC
2005
ACM
14 years 11 months ago
Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility
In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture ...
Antonio Carlos Schneider Beck, Luigi Carro
AHS
2006
IEEE
86views Hardware» more  AHS 2006»
15 years 3 months ago
An Efficient Technique for Preventing Single Event Disruptions in Synchronous and Reconfigurable Architectures
This paper presents a unique SEU (single Event Upset) mitigation technique based upon Temporal Data Sampling for synchronous circuits and configuration bit storage for programmabl...
Sajid Baloch, Tughrul Arslan, Adrian Stoica
DAC
2001
ACM
15 years 10 months ago
Re-Configurable Computing in Wireless
Wireless communications requires a new approach to implement the algorithms for new standards. The computational demands of these standards are outstripping the ability of traditi...
Bill Salefski, Levent Caglar
DAC
2002
ACM
15 years 10 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
JSS
2002
138views more  JSS 2002»
14 years 9 months ago
Architectural design and evaluation of an efficient Web-crawling system
This paper presents an architectural design and evaluation result of an efficient Web-crawling system. The design involves a fully distributed architecture, a URL allocating algor...
Hongfei Yan, Jianyong Wang, Xiaoming Li, Lin Guo