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DATE
2008
IEEE
145views Hardware» more  DATE 2008»
15 years 8 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
CODES
1999
IEEE
15 years 5 months ago
An MPEG-2 decoder case study as a driver for a system level design methodology
We present a case study on the design of a heterogeneous architecture for MPEG-2 video decoding. The primary objective of the case study is the validation of the SPADE methodology...
Pieter van der Wolf, Paul Lieverse, Mudit Goel, Da...
ICCD
2003
IEEE
112views Hardware» more  ICCD 2003»
15 years 10 months ago
Power Efficient Data Cache Designs
This paper investigates some power efficient data cache designs that try to significantly reduce the cache energy consumption, both static and dynamic, with a minimal impact in pe...
Jaume Abella, Antonio González
CASES
2007
ACM
15 years 5 months ago
Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking
We propose a technique which leverages configurable data caches to address the problem of cache interference in multitasking embedded systems. Data caches are often necessary to p...
Rakesh Reddy, Peter Petrov
CASES
2006
ACM
15 years 7 months ago
A dynamic binary instrumentation engine for the ARM architecture
Dynamic binary instrumentation (DBI) is a powerful technique for analyzing the runtime behavior of software. While numerous DBI frameworks have been developed for general-purpose ...
Kim M. Hazelwood, Artur Klauser