796 search results - page 90 / 160 » Design Space Exploration for Dynamically Reconfigurable Arch... |
125
click to vote
ICCD
1999
IEEE
15 years 5 months ago
1999
IEEE
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
105
click to vote
IEEEIAS
2008
IEEE
15 years 7 months ago
2008
IEEE
: An intrusion detection system should support the operator of the system. Thus, in addition to producing alerts, it should allow for easy insertion of new detection algorithms. It...
107
click to vote
EUC
2006
Springer
15 years 5 months ago
2006
Springer
Abstract. As process technology scales down, power wall starts to hinder improvements in processor performance. Performance optimization has to proceed under a power constraint. Th...
109
click to vote
ASPDAC
2005
ACM
15 years 3 months ago
2005
ACM
— On current superscalar processors, performance and power issues cannot be decoupled for designers. Extensive simulations are usually required to meet both power and performance...
105
click to vote
EHCI
2001
15 years 2 months ago
2001
We present a way of analyzing sensed context information formulated to help in the generation, documentation and assessment of the designs of context-aware applications. Starting w...