200 search results - page 24 / 40 » Design Time Reliability Analysis of Distributed Fault Tolera... |
97
Voted
DAC
2006
ACM
15 years 3 months ago
2006
ACM
Conventionally, signal net routing is almost always implemented as Steiner trees. However, non-tree topology is often superior on timing performance as well as tolerance to open f...
ICMCS
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper proposes a practical content-dependent lowpower DCT design with tolerable quality drop. Lowpower issue has become more and more important, especially for portable devic...
DAC
2006
ACM
16 years 19 days ago
2006
ACM
Aggressive scaling of technology has an adverse impact on the reliability of VLSI circuits. Apart from increasing transient error susceptibility, the circuits also become more vul...
80
Voted
GECCO
2005
Springer
15 years 5 months ago
2005
Springer
The size and complexity of systems based on multiple processing units demand techniques for the automatic diagnosis of their state. System-level diagnosis consists in determining ...
85
Voted
DAC
2005
ACM
15 years 1 months ago
2005
ACM
In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay distribution, it is dif...