Sciweavers

870 search results - page 155 / 174
» Design Tradeoffs for SSD Performance
Sort
View
ICCAD
2002
IEEE
141views Hardware» more  ICCAD 2002»
15 years 10 months ago
A hierarchical modeling framework for on-chip communication architectures
— The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication archite...
Xinping Zhu, Sharad Malik
FCCM
2006
IEEE
131views VLSI» more  FCCM 2006»
15 years 8 months ago
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
Nachiket Kapre, Nikil Mehta, Michael DeLorimier, R...
CODES
2009
IEEE
15 years 5 months ago
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
Vincenzo Rana, Srinivasan Murali, David Atienza, M...
GECCO
2008
Springer
163views Optimization» more  GECCO 2008»
15 years 3 months ago
Embedded evolutionary multi-objective optimization for worst case robustness
In Multi-Objective Problems (MOPs) involving uncertainty, each solution might be associated with a cluster of performances in the objective space depending on the possible scenari...
Gideon Avigad, Jürgen Branke
HPCA
2009
IEEE
16 years 2 months ago
Architectural Contesting
Previous studies have proposed techniques to dynamically change the architecture of a processor to better suit the characteristics of the workload at hand. However, all such appro...
Hashem Hashemi Najaf-abadi, Eric Rotenberg