4 search results - page 1 / 1 » Design and Analysis of a New Self-Testing Adder which Utiliz... |
79
Voted
DDECS
2007
IEEE
15 years 4 months ago
2007
IEEE
— This paper describes a new self-testing 1-bit full adder. This circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. The adder is able to detec...
92
Voted
CORR
2006
Springer
14 years 10 months ago
2006
Springer
Differential Power Analysis (DPA) presents a major challenge to mathematically-secure cryptographic protocols. Attackers can break the encryption by measuring the energy consumed i...
TC
1998
14 years 9 months ago
1998
—This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs)...
DAC
2006
ACM
15 years 11 months ago
2006
ACM
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...