761 search results - page 13 / 153 » Design and Analysis of a Robust Pipelined Memory System |
VLSID
2002
IEEE
16 years 4 days ago
2002
IEEE
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
We present a framework (Real-Time Calculus) for analysing various system properties pertaining to timing analysis, loads on various components and on-chip buffer memory requiremen...
ISSS
2002
IEEE
15 years 4 months ago
2002
IEEE
This paper presents a novel low-energy memory design technique, considering effective bitwidth of variables for applicationspecific systems, called VAbM technique. It targets th...
CODES
2009
IEEE
15 years 3 months ago
2009
IEEE
In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accu...
SPAA
2000
ACM
15 years 4 months ago
2000
ACM
This paper presents mathematical foundations for the design of a memory controller subcomponent that helps to bridge the processor/memory performance gap for applications with str...