761 search results - page 91 / 153 » Design and Analysis of a Robust Pipelined Memory System |
MICRO
2006
IEEE
15 years 3 months ago
2006
IEEE
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
106
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ISCA
1995
IEEE
15 years 1 months ago
1995
IEEE
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
CODES
2006
IEEE
15 years 4 months ago
2006
IEEE
Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication net...
EUROSSC
2007
Springer
15 years 4 months ago
2007
Springer
This paper addresses the design of a large area, high resolution, networked pressure sensing floor with primary application in movement-based human-computer interaction (M-HCI). T...
SIGSOFT
2005
ACM
15 years 10 months ago
2005
ACM
The continuous requirements of evolving a delivered software system and the rising cost of shutting down a running software system are forcing researchers and practitioners to fin...