150 search results - page 11 / 30 » Design and CAD for 3D integrated circuits |
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
: Scaling down in very deep submicron (VDSM) technologies increases the delay, power consumption of on-chip interconnects, while the reliability and yield decrease. In high perform...
179
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DAC
2011
ACM
13 years 9 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
ISLPED
2006
ACM
15 years 3 months ago
2006
ACM
All existing methods for thermal-via allocation are based on a steady-state thermal analysis and may lead to excessive number of thermal vias. This paper develops an accurate and ...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract—This work proposes reliability aware through silicon via (TSV) planning for the 3D stacked silicon integrated circuits (ICs). The 3D power distribution network is modele...
103
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3DIC
2009
IEEE
15 years 4 months ago
2009
IEEE
The first memristor, originally theorized by Dr. Leon Chua in 1971, was identified by a team at HP Labs in 2008. This new fundamental circuit element is unique in that its resis...