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» Design and CAD for 3D integrated circuits
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ISLPED
2005
ACM
91views Hardware» more  ISLPED 2005»
15 years 3 months ago
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs
As FPGAs enter the nanometer regime, several modifications are needed to reduce the increasing leakage power dissipation. Hence, this work presents some modifications to the FPG...
Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
ISQED
2003
IEEE
96views Hardware» more  ISQED 2003»
15 years 3 months ago
New DFM Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains
Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains Pradiptya Ghosh, Chung-shin Kang, Michael Sanie and David Pinto Numerical Technologies, 70 West P...
Pradiptya Ghosh, Chung-shin Kang, Michael Sanie, D...
ICCAD
2006
IEEE
139views Hardware» more  ICCAD 2006»
15 years 6 months ago
Analog placement with symmetry and other placement constraints
In order to handle device matching in analog circuits, some pairs of modules are required to be placed symmetrically. This paper addresses this device-level placement problem for ...
Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N...
GLVLSI
2003
IEEE
177views VLSI» more  GLVLSI 2003»
15 years 3 months ago
Congestion reduction in traditional and new routing architectures
In dense integrated circuit designs, management of routing congestion is essential; an over congested design may be unroutable. Many factors influence congestion: placement, rout...
Ameya R. Agnihotri, Patrick H. Madden
FPGA
2003
ACM
125views FPGA» more  FPGA 2003»
15 years 3 months ago
I/O placement for FPGAs with multiple I/O standards
In this paper, we present the first exact algorithm to solve the constrained I/O placement problem for FPGAs that support multiple I/O standards. We derive a compact integer line...
Wai-Kei Mak