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» Design and CAD for 3D integrated circuits
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DAC
2006
ACM
15 years 10 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...
DAC
2012
ACM
13 years 5 days ago
Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs
Due to the large geometry of through-silicon-vias (TSVs) and their connections to the power grid, significant current crowding can occur in 3D ICs. Prior works model TSVs and pow...
Xin Zhao, Michael Scheuermann, Sung Kyu Lim
ASPDAC
2012
ACM
279views Hardware» more  ASPDAC 2012»
13 years 5 months ago
Block-level 3D IC design with through-silicon-via planning
— Since re-designing and re-optimizing existing logic, memory, and IP blocks in a 3D fashion significantly increases design cost, nearterm three-dimensional integrated circuit (...
Dae Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim
DAC
2011
ACM
13 years 9 months ago
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC
This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed based on the proposed coupling model. Analysis results show that TSVs cause significan...
Chang Liu, Taigon Song, Jonghyun Cho, Joohee Kim, ...
GLVLSI
2003
IEEE
180views VLSI» more  GLVLSI 2003»
15 years 3 months ago
3D direct vertical interconnect microprocessors test vehicle
The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated C...
John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan...