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LCTRTS
2005
Springer
13 years 12 months ago
Complementing software pipelining with software thread integration
Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in highperformance embedded applications such as digital sign...
Won So, Alexander G. Dean
SPAA
2006
ACM
14 years 9 days ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
ICCAD
2008
IEEE
108views Hardware» more  ICCAD 2008»
14 years 3 months ago
FBT: filled buffer technique to reduce code size for VLIW processors
— VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated...
Talal Bonny, Jörg Henkel
ICS
2005
Tsinghua U.
13 years 12 months ago
Disk layout optimization for reducing energy consumption
Excessive power consumption is becoming a major barrier to extracting the maximum performance from high-performance parallel systems. Therefore, techniques oriented towards reduci...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir
ERSHOV
1989
Springer
13 years 10 months ago
Experiments with Implementations of Two Theoretical Constructions
This paper reports two experiments with implementations of constructions from theoretical computer science. The first one deals with Kleene’s and Rogers’ second recursion the...
Torben Amtoft Hansen, Thomas Nikolajsen, Jesper La...