Sciweavers

1084 search results - page 183 / 217
» Design and Evaluation of a Selective Compressed Memory Syste...
Sort
View
CCGRID
2009
IEEE
15 years 6 months ago
Improving Parallel Write by Node-Level Request Scheduling
In a cluster of multiple processors or cpu-cores, many processes may run on each compute node. Each process tends to issue contiguous I/O requests for snapshot, checkpointing or s...
Kazuki Ohta, Hiroya Matsuba, Yutaka Ishikawa
SENSYS
2005
ACM
15 years 5 months ago
A new approach for establishing pairwise keys for securing wireless sensor networks
Wireless sensor networks based on highly resource-constrained devices require symmetric cryptography in order to make them secure. Integral to this is the exchange of unique symme...
Arno Wacker, Mirko Knoll, Timo Heiber, Kurt Rother...
HPCA
1998
IEEE
15 years 4 months ago
Performance Study of a Concurrent Multithreaded Processor
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen-Chu...
CCGRID
2004
IEEE
15 years 3 months ago
Unifier: unifying cache management and communication buffer management for PVFS over InfiniBand
The advent of networking technologies and high performance transport protocols facilitates the service of storage over networks. However, they pose challenges in integration and i...
Jiesheng Wu, Pete Wyckoff, Dhabaleswar K. Panda, R...
FPL
2006
Springer
124views Hardware» more  FPL 2006»
15 years 3 months ago
A Dynamically Reconfigurable Queue Scheduler
In this paper we present the design and implementation of a dynamically reconfigurable system for packet queue scheduling. Two widely accepted queue schedulers have been implement...
Christoforos Kachris, Stamatis Vassiliadis