335 search results - page 17 / 67 » Design and Implementation of Parallel Modified PrefixSpan Me... |
107
Voted
VLSID
2001
IEEE
16 years 1 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
117
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ICCAD
2009
IEEE
14 years 10 months ago
2009
IEEE
A parallel computing approach for large-scale SPICE-accurate circuit simulation is described that is based on a new preconditioned iterative solver. The preconditioner involves the...
115
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GLVLSI
2003
IEEE
15 years 6 months ago
2003
IEEE
Design and implementation of a fast parallel architecture based on an improved principal component analysis (PCA) method called Composite PCA suitable for real-time face recogniti...
ASAP
2007
IEEE
15 years 7 months ago
2007
IEEE
A hardware-oriented method for evaluating complex polynomials by solving iteratively a system of linear equations is proposed. Its implementation uses a digit-serial iterations on...
106
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CANPC
1999
Springer
15 years 5 months ago
1999
Springer
Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best perfo...