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» Design and Implementation of Real-Time Transactional Memory
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RTCSA
2007
IEEE
15 years 3 months ago
A NOR Emulation Strategy over NAND Flash Memory
This work is motivated by a strong market demand in the replacement of NOR flash memory with NAND flash memory to cut down the cost in many embedded-system designs, such as mobi...
Jian-Hong Lin, Yuan-Hao Chang, Jen-Wei Hsieh, Tei-...
ICPP
1999
IEEE
15 years 1 months ago
A Bandwidth-Efficient Implementation of Mesh with Multiple Broadcasting
This paper presents a mesh with virtual buses as the bandwidth-efficient implementation of the mesh with multiple broadcasting on which many computational problems can be solved w...
Jong Hyuk Choi, Bong Wan Kim, Kyu Ho Park, Kwang-I...
DATE
2003
IEEE
117views Hardware» more  DATE 2003»
15 years 2 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen
VLDB
2004
ACM
126views Database» more  VLDB 2004»
15 years 3 months ago
STEPS towards Cache-resident Transaction Processing
Online transaction processing (OLTP) is a multibillion dollar industry with high-end database servers employing state-of-the-art processors to maximize performance. Unfortunately,...
Stavros Harizopoulos, Anastassia Ailamaki
ICS
2009
Tsinghua U.
15 years 2 months ago
Dynamic task set partitioning based on balancing memory requirements to reduce power consumption
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...