47 search results - page 2 / 10 » Design and Implementation of Scalable Low-Power Montgomery M... |
DAC
2005
ACM
14 years 11 months ago
2005
ACM
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...
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Voted
GLVLSI
2007
IEEE
15 years 1 months ago
2007
IEEE
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
GLOBECOM
2007
IEEE
14 years 11 months ago
2007
IEEE
: The improvement of spectral efficiency comes at the cost of exponential increment of signal processing complexity [1]. Hence, the energy-efficiency of baseband has recently turne...
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
— High secure cryptographic systems require large bit-length encryption keys which presents a challenge to their efficient hardware implementation especially in embedded devices...
ISLPED
2000
ACM
15 years 1 months ago
2000
ACM
In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Variou...