Sciweavers

243 search results - page 3 / 49
» Design and Implementation of a CFAR Processor for Target Det...
Sort
View
FPL
2004
Springer
106views Hardware» more  FPL 2004»
13 years 11 months ago
FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications
ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffer from fixed hardware after design, while ASIPs and reconf...
Leandro Möller, Ney Laert Vilar Calazans, Fer...
ASAP
2007
IEEE
134views Hardware» more  ASAP 2007»
13 years 8 months ago
Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications
Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, ...
David Montgomery, Ali Akoglu
VLSID
2005
IEEE
167views VLSI» more  VLSID 2005»
14 years 6 months ago
A Methodology and Tooling Enabling Application Specific Processor Design
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
Andreas Hoffmann, Frank Fiedler, Achim Nohl, Suren...
DATE
2006
IEEE
90views Hardware» more  DATE 2006»
14 years 8 days ago
A time predictable Java processor
This paper presents a Java processor, called JOP, designed for time-predictable execution of real-time tasks. JOP is the implementation of the Java virtual machine in hardware. We...
Martin Schoeberl
KBSE
2005
IEEE
13 years 11 months ago
Designing and implementing a family of intrusion detection systems
Intrusion detection systems are distributed applications that analyze the events in a networked system to identify malicious behavior. The analysis is performed using a number of ...
Richard A. Kemmerer