243 search results - page 3 / 49 » Design and Implementation of a CFAR Processor for Target Det... |
FPL
2004
Springer
13 years 11 months ago
2004
Springer
ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffer from fixed hardware after design, while ASIPs and reconf...
ASAP
2007
IEEE
13 years 8 months ago
2007
IEEE
Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, ...
VLSID
2005
IEEE
14 years 6 months ago
2005
IEEE
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
DATE
2006
IEEE
14 years 8 days ago
2006
IEEE
This paper presents a Java processor, called JOP, designed for time-predictable execution of real-time tasks. JOP is the implementation of the Java virtual machine in hardware. We...
KBSE
2005
IEEE
13 years 11 months ago
2005
IEEE
Intrusion detection systems are distributed applications that analyze the events in a networked system to identify malicious behavior. The analysis is performed using a number of ...