Sciweavers

1224 search results - page 149 / 245
» Design and Implementation of a Practical Parallel Delaunay A...
Sort
View
DCOSS
2006
Springer
15 years 8 months ago
Efficient In-Network Processing Through Local Ad-Hoc Information Coalescence
We consider in-network processing via local message passing. The considered setting involves a set of sensors each of which can communicate with a subset of other sensors. There is...
Onur Savas, Murat Alanyali, Venkatesh Saligrama
STTT
2010
115views more  STTT 2010»
15 years 3 months ago
Scalable shared memory LTL model checking
Recent development in computer hardware has brought more wide-spread emergence of shared memory, multi-core systems. These architectures offer opportunities to speed up various ta...
Jiri Barnat, Lubos Brim, Petr Rockai
ASAP
2003
IEEE
153views Hardware» more  ASAP 2003»
15 years 10 months ago
Hardware Synthesis for Multi-Dimensional Time
This paper introduces basic principles for extending the classical systolic synthesis methodology to multi-dimensional time. Multi-dimensional scheduling enables complex algorithm...
Anne-Claire Guillou, Patrice Quinton, Tanguy Risse...
IPPS
2003
IEEE
15 years 10 months ago
Grid Harvest Service: A System for Long-Term, Application-Level Task Scheduling
With the emergence of grid computing environment, performance measurement, analysis and prediction of non-dedicated distributed systems have become increasingly important. In this...
Xian-He Sun, Ming Wu
ICCS
2007
Springer
15 years 11 months ago
A Combined Hardware/Software Optimization Framework for Signal Representation and Recognition
This paper describes a signal recognition system that is jointly optimized from mathematical representation, algorithm design and final implementation. The goal is to exploit sign...
Melina Demertzi, Pedro C. Diniz, Mary W. Hall, Ann...