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DAGSTUHL
2007
15 years 1 months ago
Parallelism through Digital Circuit Design
Abstract. Two ways to exploit chips with a very large number of transistors are multicore processors and programmable logic chips. Some data parallel algorithms can be executed eļ¬...
John O'Donnell
DATE
2006
IEEE
125views Hardware» more  DATE 2006»
15 years 5 months ago
Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)
In this paper we analyze a 3D image rendering algorithm and the different mapping schemes to implement it in a SIMD reconfigurable architecture. 3D image render is highly computat...
Javier Davila, Alfonso de Torres, Jose Manuel Sanc...
164
Voted
WAE
2001
281views Algorithms» more  WAE 2001»
15 years 1 months ago
Using PRAM Algorithms on a Uniform-Memory-Access Shared-Memory Architecture
The ability to provide uniform shared-memory access to a significant number of processors in a single SMP node brings us much closer to the ideal PRAM parallel computer. In this pa...
David A. Bader, Ajith K. Illendula, Bernard M. E. ...
FPGA
2006
ACM
224views FPGA» more  FPGA 2006»
15 years 3 months ago
Flexible implementation of genetic algorithms on FPGAs
In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture for GA which consist...
Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shiba...
IPPS
2008
IEEE
15 years 6 months ago
Portioned static-priority scheduling on multiprocessors
This paper proposes an efficient real-time scheduling algorithm for multiprocessor platforms. The algorithm is a derivative of the Rate Monotonic (RM) algorithm, with its basis on...
Shinpei Kato, Nobuyuki Yamasaki