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SIGMETRICS
2003
ACM
147views Hardware» more  SIGMETRICS 2003»
15 years 5 months ago
Effect of node size on the performance of cache-conscious B+-trees
In main-memory databases, the number of processor cache misses has a critical impact on the performance of the system. Cacheconscious indices are designed to improve performance b...
Richard A. Hankins, Jignesh M. Patel
CSFW
2006
IEEE
15 years 6 months ago
Encoding Information Flow in Haskell
This paper presents an embedded security sublanguage for enforcing information-flow policies in the standard Haskell programming language. The sublanguage provides useful informa...
Peng Li, Steve Zdancewic
SAINT
2005
IEEE
15 years 5 months ago
A Context-centric Security Middleware for Service Provisioning in Pervasive Computing
Pervasive user mobility, wireless connectivity and the widespread diffusion of portable devices raise new challenges for ubiquitous service provisioning. An emerging architecture ...
Antonio Corradi, Rebecca Montanari, Daniela Tibald...
ICCAD
1993
IEEE
104views Hardware» more  ICCAD 1993»
15 years 4 months ago
Parallel timing simulation on a distributed memory multiprocessor
Circuit simulation is one of the most computationally expensive tasks in circuit design and optimization. Detailed simulation at the level of precision of SPICE is usually perform...
Chih-Po Wen, Katherine A. Yelick
CORR
2010
Springer
150views Education» more  CORR 2010»
14 years 12 months ago
Boosting Multi-Core Reachability Performance with Shared Hash Tables
Abstract--This paper focuses on data structures for multicore reachability, which is a key component in model checking algorithms and other verification methods. A cornerstone of a...
Alfons Laarman, Jaco van de Pol, Michael Weber 000...